1. Field of the Invention
The present invention relates to an amorphous silicon thin film transistor and a shift register having the amorphous-silicon thin film transistor, and more particularly to an amorphous-silicon thin film transistor having reduced parasitic capacitance and a shift register having the amorphous-silicon thin film transistor.
2. Description of the Related Art
A liquid crystal display device is equipped with a gate driver integrated circuit (IC). The gate driver integrated circuit is mounted on a liquid crystal display panel as a tape carrier package (TCP) or via a chip-on-glass (COG) manner. However, the liquid crystal display device equipped with the gate driver integrated circuit has some disadvantages such as high manufacturing cost and a structural hindrance for designing the liquid crystal display device. Thus, a liquid crystal display device having no gate driver integrated circuit has been developed. The gate driver integrated circuit may be embodied using the process of manufacturing amorphous-silicon thin film transistor.
One example of a shift register circuit including amorphous-silicon thin film transistors is disclosed in U.S. Pat. No. 5,517,542. The shift register circuit disclosed in the U.S. patent includes seven amorphous-silicon thin film transistors.
FIG. 1 is a circuit diagram showing a stage of a conventional shift register. The stage of the conventional shift register is disclosed in the above U.S. patent. The conventional shift register replaces the gate driver integrated circuit.
Referring to FIG. 1, each of the stages of the shift register includes a pull-up part 110, a pull-down part 120, a pull-up driver part 130 and a pull-down driver part 140. The shift register receives a gate line driving signal GOUTN-1 of a previous stage (or scan start signal STY, when the stage is a first stage), and the shift register generates a gate line driving signal GOUTN (or scan signal). When a stage is a first stage of the shift register, the first stage receives the scan start signal STY generated from a timing controller (not shown), and generates a first gate line driving signal GOUTL′ When the stage is a second stage of the shift register, the second stage receives the first gate line driving signal GOUT1 generated from the first stage, and generates a second gate line driving signal GOUT2. Likewise, when the stage is an Nth stage, the stage receives a (N−1)th gate line driving signal GOUTN_1 generated from a (N−1) th stage, and generates a Nth gate line driving signal GOUTN.
The shift registers are integrated in a thin film transistor liquid crystal display panel so as to perform the same operation of the gate driver integrated circuit.
The shift resisters are integrated in a thin film transistor liquid crystal display panel so as to perform the same operation of the gate driver integrated circuit.
FIG. 2 is a block diagram showing a gate driver circuit including a state of FIG. 1.
Referring to FIGS. 1 and 2, a gate driver circuit 174 generates gate line driving signals GOUT1, GOUT2, . . . , GOUTN. The gate driver circuit 174 includes N stages.
A first stage SRC1 receives a scan start signal STV generated from the timing controller (not shown), a gate turn-on voltage VON, a gate turn-off voltage VOFF and a first power clock signal CKV. The first stage SRC1 generates a first gate line driving signal GOUT1 for selecting a first gate line.
A second stage SRC2 receives the first gate line driving signal GOUT1 generated from the first stage SRC1, the gate turn-on voltage VON, the gate turn-off voltage VOFF, and a second power clock signal CKVB. The second stage SRC2 generates a second gate line driving signal GOUT2 for selecting a second gate line.
Likewise, an Nth stage SRCN receives a (N−1)th gate line driving signal GOUTN-1 generated form the (N−1)th stage, the gate turn-on voltage VON, the gate turn-off voltage VOFF and the first power clock signal CKV or the second power clock signal CKVB. The Nth stage SRCN generates an Nth gate line driving signal GOUTN for selecting an Nth gate line.
FIG. 3A is a logic diagram showing a stage of a shift register of FIG. 1, FIG. 3B is a timing diagram showing an operation of a stage, and FIG. 3C is a partial circuit diagram showing a virtual parasitic capacitor electrically coupled to a pull-up transistor of FIG. 1.
Referring to FIG. 3A, an unit stage may be expressed as the equivalent circuit including a S/R latch 21 and an AND-gate 22. A timing diagram of FIG. 3B shows an operation of the unit stage.
The S/R latch 21 may be embodied in various forms. A pull-down transistor, which outputs a clock signal CK1 in response to an output value Q generated from the S/R latch 21, is essential.
Referring again to FIG. 1, an NMOS transistor Q1 of the pull-up part 110 includes an amorphous-silicon. Therefore, the NMOS transistor Q1 of the pull-up part 110 has very large transistor size because a large amplitude of voltage (for example, from −14V to 20V) should be applied to the NMOS transistor Q1 due to the very small electron mobility of the amorphous-silicon of the NMOS transistor Q1 so as to drive the liquid crystal display device having a large screen size. For example, in liquid crystal display panel having a screen size of 12.1 inch (XGA), a parasitic capacitance of a gate line has a value from about 250 pF to about 300 pF. Therefore, in order to drive an amorphous-silicon thin film transistor designed in accordance with minimum design rule 4 μm, a channel width of the amorphous-silicon thin film transistor should be about 5500 μm when a channel length of the amorphous-silicon thin film transistor is about 4 μm.
Therefore, a parasitic capacitance Cgd between a gate electrode and a drain electrode of the NMOS amorphous-silicon thin film transistor Q1 increases. The value of the parasitic capacitance is about 3 pF. This value causes a mal-function of the gate driver circuit employing the NMOS amorphous-silicon thin film transistor.
The reason of the mal-function is as follows. The parasitic capacitor Cgd is electrically connected with a terminal to which a clock signal CK1 (the first power clock signal CKV or the second power clock signal CKVB) having a large amplitude of voltage (for example, from about −14V to about 20V) is applied, and the parasitic capacitor Cgd is electrically connected between the drain and gate electrodes of the NMOS amorphous-silicon thin film transistor Q1 to apply undesired voltage signal to the gate electrode of the NMOS amorphous-silicon thin film transistor Q1. For example, when there exists no holding transistor for maintaining the voltage level of the gate electrode of the NMOS amorphous-silicon thin film transistor Q1 at the gate turn-off voltage VOFF, the power clock signal (CKV or CKVB) is applied to the gate electrode of the NMOS amorphous-silicon thin film transistor Q1. Therefore, a voltage of the gate electrode is from about −14V to about 20V, an output signal equals to 20−Vth(V) (maximum value minus threshold voltage of the NMOS amorphous-silicon transistor), and the output signal is applied to the gate line of the liquid crystal display panel. Therefore, abnormal image display may occur.
In order to maintain the voltage level of the gate electrode of the pull-up transistor Q1 (NMOS amorphous-silicon thin film transistor) at the gate turn-off voltage state VOFF, a hold transistor Q5 is essential. The hold transistor Q5 is an amorphous-silicon thin film transistor. A pull-down thin film transistor Q2 performs a pull down function where the scan signal is maintained at gate turn-off voltage VOFF in most of the period after the pull-up transistor Q1 operates.
The parasitic capacitor Cgd has large capacitance and is electrically coupled to the terminal to which the clock pulse CK (from about −14V to about 20V). Therefore, in order to maintain a gate electrode of the pull-up transistor Q1 or the pull-down transistor Q2 at a lower voltage than the threshold voltage Vth of the pull-up transistor Q1 or the pull-down transistor Q2, the hold transistor Q5 should have a large transistor size. Hereinafter, a transistor size is referred to as the ratio (W/L) of a channel width (W) of the transistor with respect to a channel length (L) of the transistor.
It is hard to form the hold transistor Q5 having a large transistor size in a region of narrow black matrix or in a region of seal-line. Further, when the hold transistor Q5 is deteriorated, a display quality of a liquid crystal display device may be lowered.